Referring to FIG. 1, a register access controller 100 of the prior art controls the transfer of data between a register page 102 and a bus interface 104. In addition, data is also transferred between the bus interface 104 and an electronic device 106 accessing the page of registers 102. The register page 102 is comprised of a plurality of registers including a first register 111, a second register 112, a third register 113, and so on, up to an eighth register 118, and further so on, up to a sixty-fourth register 164.
In the register page 102, the first register 111 up to the eighth register 118 are implemented to store useful data. The rest of the registers (i.e., a ninth register up to the sixty-fourth register 164) are non-implemented but are included within the register page 102 in case of data processing expansion requiring more registers in the future.
Referring to FIG. 1, each register has a respective output driver coupled between that register and the bus interface 104. In FIG. 1, a first output driver 121 is coupled between the first register 111 and the bus interface 104, a second output driver 122 is coupled between the second register 112 and the bus interface 104, and so on, with an eighth output driver 128 being coupled between the eighth register 118 and the bus interface 104, and further so on, with a sixty-fourth output driver 166 being coupled between the sixty-fourth register 164 and the bus interface 104. (Note that the total number of registers and the total number of implemented registers are considerably larger for typical register pages, but eight implemented registers within the register page 102 having a total of 64 registers are shown in FIG. 1 for clarity of illustration.)
Each output driver turns on to couple the respective register corresponding to that output driver to the bus interface 104 or turns off to decouple the respective register to the bus interface 104. A 6-bit address line 170 indicates a selected register of the 64 registers of the register page 102 for being coupled to the bus interface 104. A full spectrum address decoder 172 decodes the data on the 6-bit address line 170 and generates a first control signal which turns on the respective output driver of the selected register. In FIG. 1, the first control signal may be a high state at an output line coupled to the respective output driver of the selected register and a low state at output lines coupled to the respective output driver of the rest of the plurality of registers of the register page 102.
The first register 111 through the eighth register 118 are implemented to contain useful data to be transferred between any of those implemented registers and the electronic device 106. On the other hand, the content of a non-implemented register (i.e. any of the ninth register through the sixty-fourth register 164) are not useful for data processing and is typically comprised of a predetermined bit pattern (such as a series of low bits, i.e., "0 0 0 . . . ") to indicate to the electronic device 106 that such a register is non-implemented.
Since the content of the implemented registers are useful, the full spectrum address decoder 172 which has circuitry to decode the full 6 bits for selecting any of all 64 registers is not necessary. Since only the first register 111 through the eighth register 118 are implemented, a simpler 3 bit partial spectrum address decoder is sufficient. Such a partial spectrum address decoder which decodes only 3 bits of the 6 bits may have a smaller and a simpler decoding circuitry and thus may provide decoding with a faster response time as is known to one of ordinary skill in the art of digital systems design.
Referring to FIG. 2, another register access controller 200 of the prior art includes such a partial spectrum address decoder 202. (Note that elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function.) This partial spectrum address decoder may decode only the 3 least significant bits of the 6 bits on the address line 170 for the eight implemented registers within the register page 102.
However, with the register access controller 200 of the prior art, if the 6 bits on the address line 170 specify a non-implemented register within the register page 102, then the bus interface 104 is not claimed by any of the registers. The electronic device 106 receives no response in that case. Such a condition is commonly referred to as a "live-lock condition," and may cause adverse effects within the electronic device 106. Yet, using the partial spectrum address decoder 202 instead of the full spectrum address decoder 172 of FIG. 1 is desirable because of the advantages of a smaller and simpler decoding circuitry and a quicker response time of a partial spectrum address decoder.